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?2001 silicon storage technology, inc. s71160-05-000 5/01 505 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. ssf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit (x8) small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 features: ? organized as 64k x8 / 128k x8 / 256k x8 / 512k x8 single voltage read and write operations ? 5.0v-only for sst29sf512/010/020/040 ? 2.7-3.6v for sst29vf512/010/020/040 superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention low power consumption: ? active current: 10 ma (typical) ? standby current: 30 ? (typical) for sst29sf512/010/020/040 1 ? (typical) for sst29vf512/010/020/040 sector-erase capability ? uniform 128 byte sectors fast read access time: ? 55 ns ? 70 ns latched address and data fast erase and byte-program: ? sector-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? byte-program time: 14 ? (typical) ? chip rewrite time: 1 second (typical) for sst29sf/vf512 2 seconds (typical) for sst29sf/vf010 4 seconds (typical) for sst29sf/vf020 8 seconds (typical) for sst29sf/vf040 automatic write timing ? internal v pp generation end-of-write detection ? toggle bit ? data# polling ttl i/o compatibility for sst29sfxxx cmos i/o compatibility for sst29vfxxx jedec standard ? flash eeprom pinouts and command sets packages available ? 32-pin plcc ? 32-pin tsop (8mm x 14mm) ? 32-pin pdip product description the sst29sf512/010/020/040 and sst29vf512/010/ 020/040 are 64k x8 / 128k x8 / 256k x8 / 512k x8 cmos small-sector flash (ssf) manufactured with sst ? s propri- etary, high performance cmos superflash technology. the split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst29sfxxx devices write (program or erase) with a 4.5-5.5v power supply. the sst29vfxxx devices write (program or erase) with a 2.7- 3.6v power supply. these devices conform to jedec stan- dard pinouts for x8 memories. featuring high performance byte-program, the sst29sfxxx and sst29vfxxx devices provide a maxi- mum byte-program time of 20 ?ec. to protect against inadvertent write, they have on-chip hardware and soft- ware data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of at least 10,000 cycles. data retention is rated at greater than 100 years. the sst29sfxxx and sst29vfxxx devices are suited for applications that require convenient and economical updat- ing of program, configuration, or data memory. for all sys- tem applications, they significantly improve performance and reliability, while lowering power consumption. they inherently use less energy during erase and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the super- flash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. they also improve flexibility while lowering the cost for program, data, and configuration storage appli- cations. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. to meet high density, surface mount requirements, the sst29sfxxx and sst29vfxxx devices are offered in 32- pin plcc and 32-pin tsop packages. a 600 mil, 32-pin pdip is also offered for sst29sfxxx devices. see figures 1, 2, and 3 for pinouts. sst29sf/vf512 / 010 / 020 / 0405.0 & 2.7v 512kb / 1mb / 2mb / 4mb (x8) byte-program, small erase sector flash memories
2 preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 2001 silicon storage technology, inc. s71160-05-000 5/01 505 device operation commands are used to initiate the memory operation func- tions of the device. commands are written to the device using standard microprocessor write sequences. a com- mand is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. read the read operation of the sst29sfxxx and sst29vfxxx devices are controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing dia- gram for further details (figure 4). byte-program operation the sst29sfxxx and sst29vfxxx devices are pro- grammed on a byte-by-byte basis. the program operation consists of three steps. the first step is the three-byte-load sequence for software data protection. the second step is to load byte address and byte data. during the byte-pro- gram operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal pro- gram operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the program operation, once initiated, will be completed, within 20 ?. see figures 5 and 6 for we# and ce# controlled program operation timing diagrams and figure 16 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands written during the internal program operation will be ignored. sector-erase operation the sector-erase operation allows the system to erase the device on a sector-by-sector basis. the sst29sfxxx and sst29vfxxx offer sector-erase mode. the sector archi- tecture is based on uniform sector size of 128 bytes. the sector-erase operation is initiated by executing a six-byte- command sequence with sector-erase command (20h) and sector address (sa) in the last bus cycle. the sector address is latched on the falling edge of the sixth we# pulse, while the command (20h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase opera- tion can be determined using either data# polling or toggle bit methods. see figure 9 for timing waveforms. any com- mands issued during the sector-erase operation are ignored. chip-erase operation the sst29sfxxx and sst29vfxxx devices provide a chip-erase operation, which allows the user to erase the entire memory array to the ? 1s ? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte software data protection command sequence with chip-erase command (10h) with address 555h in the last byte sequence. the internal erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the internal erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 10 for timing diagram, and figure 19 for the flowchart. any commands written during the chip- erase operation will be ignored. write operation status detection the sst29sfxxx and sst29vfxxx devices provide two software means to detect the completion of a write (pro- gram or erase) cycle, in order to optimize the system write cycle time. the software detection includes two sta- tus bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we# which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid.
preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 3 2001 silicon storage technology, inc. s71160-05-000 5/01 505 data# polling (dq 7 ) when the sst29sfxxx and sst29vfxxx devices are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. the device is then ready for the next operation. dur- ing internal erase operation, any attempt to read dq 7 will produce a ? 0 ? . once the internal erase operation is com- pleted, dq 7 will produce a ? 1 ? . the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for pro- gram operation. for sector- or chip-erase, the data# poll- ing is valid after the rising edge of sixth we# (or ce#) pulse. see figure 7 for data# polling timing diagram and figure 17 for a flowchart. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. when the internal program or erase operation is completed, the toggling will stop. the device is then ready for the next operation. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector or chip- erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 8 for toggle bit timing dia- gram and figure 17 for a flowchart. data protection the sst29sfxxx and sst29vfxxx devices provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 2.5v for sst29sfxxx. the write operation is inhibited when v dd is less than 1.5v. for sst29vfxxx. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the sst29sfxxx and sst29vfxxx provide the jedec approved software data protection scheme for all data alteration operation, i.e., program and erase. any program operation requires the inclusion of a series of three byte sequence. the three byte-load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power- up or power-down. any erase operation requires the inclu- sion of six byte load sequence. these devices are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. dur- ing sdp command sequence, invalid commands will abort the device to read mode, within t rc . product identification the product identification mode identifies the devices as sst29sf512, sst29sf010, sst29sf020, sst29sf040 and sst29vf512, sst29vf010, sst29vf020, sst29vf040 and manufacturer as sst. this mode may be accessed by software operations. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufactur- ers in the same socket. for details, see table 4 for software operation, figure 11 for the software id entry and read timing diagram and figure 18 for the software id entry command sequence flowchart. product identification mode exit/reset in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read operation. please note that the software id exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 12 for timing wave- form and figure 18 for a flowchart. table 1: p roduct i dentification address data manufacturer ? s id 0000h bfh device id sst29sf512 0001h 20h sst29vf512 0001h 21h sst29sf010 0001h 22h sst29vf010 0001h 23h sst29sf020 0001h 24h sst29vf020 0001h 25h sst29sf040 0001h 13h sst29vf040 0001h 14h t1.1 505
4 preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 2001 silicon storage technology, inc. s71160-05-000 5/01 505 figure 1: p in a ssignments for 32- pin plcc y-decoder i/o buffers and data latches 505 ill b1.1 address buffers & latches x-decoder dq 7 - dq 0 memory address oe# ce# we# superflash memory control logic f unctional b lock d iagram 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a14 a13 a8 a9 a11 oe# a10 ce# dq7 4 3 2 1 32 31 30 a12 a15 nc nc v dd we# nc a12 a15 a16 nc v dd we# nc a12 a15 a16 nc v dd we# a17 a12 a15 a16 a18 v dd we# a17 32-pin plcc top view 505 ill f02a.3 14 15 16 17 18 19 20 dq1 dq2 v ss dq3 dq4 dq5 dq6 dq1 dq2 v ss dq3 dq4 dq5 dq6 dq1 dq2 v ss dq3 dq4 dq5 dq6 dq1 dq2 v ss dq3 dq4 dq5 dq6 sst29sf/vf512 sst29sf/vf010 sst29sf/vf020 sst29sf/vf040 sst29sf/vf010 sst29sf/vf020 sst29sf/vf040 sst29sf/vf512 sst29sf/vf512 sst29sf/vf010 sst29sf/vf020 sst29sf/vf040 sst29sf/vf010 sst29sf/vf020 sst29sf/vf040 sst29sf/vf512
preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 5 2001 silicon storage technology, inc. s71160-05-000 5/01 505 figure 2: p in a ssignments for 32- pin tsop (8 mm x 14 mm ) figure 3: p in a ssignments for 32- pin pdip a11 a9 a8 a13 a14 nc we# v dd nc nc a15 a12 a7 a6 a5 a4 a11 a9 a8 a13 a14 nc we# v dd nc a16 a15 a12 a7 a6 a5 a4 a11 a9 a8 a13 a14 a17 we# v dd nc a16 a15 a12 a7 a6 a5 a4 a11 a9 a8 a13 a14 a17 we# v dd a18 a16 a15 a12 a7 a6 a5 a4 sst29sf/vf512 sst29sf/vf010 sst29sf/vf020 sst29sf/vf040 sst29sf/vf010 sst29sf/vf020 sst29sf/vf040 sst29sf/vf512 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 505 ill f01.2 standard pinout top view die up 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin pdip top view 505 ill f02b.4 nc nc a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v dd we# nc a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v dd we# nc a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v dd we# a17 a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v dd we# a17 a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 sst29sf512 sst29sf010 sst29sf020 sst29sf040 sst29sf010 sst29sf020 sst29sf040 sst29sf512
6 preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 2001 silicon storage technology, inc. s71160-05-000 5/01 505 table 2: p in d escription symbol pin name functions a ms 1 -a 0 address inputs to provide memory addresses. during sector-erase a ms -a 8 address lines will select the sector. dq 7 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 4.5-5.5v for sst29sf512/010/020/040 2.7-3.6v for sst29vf512/010/020/040 v ss ground nc no connection pin not connected internally t2.3 505 1. a ms = most significant address a ms = a 15 for sst29sf/vf512, a 16 for sst29sf/vf010, a 17 for sst29sf/vf020, and a 18 for sst29sf/vf040 table 3: o peration m odes s election mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector address, xxh for chip-erase standby v ih xxhigh z x write inhibit x v il xhigh z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 4 t3.4 505
preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 7 2001 silicon storage technology, inc. s71160-05-000 5/01 505 table 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data byte-program 555h aah 2aah 55h 555h a0h ba 2 data sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 3 20h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h software id entry 4,5 555h aah 2aah 55h 555h 90h software id exit 6 xxh f0h software id exit 6 555h aah 2aah 55h 555h f0h t4.4 505 1. address format a 14 -a 0 (hex), address a 15 can be v il or v ih , but no other value, for the command sequence for sst29sf/vf512. addresses a 15 - a 16 can be v il or v ih , but no other value, for the command sequence for sst29sf/vf010. addresses a 15 - a 17 can be v il or v ih , but no other value, for the command sequence for sst29sf/vf020. addresses a 15 - a 18 can be v il or v ih , but no other value, for the command sequence for sst29sf/vf040. 2. ba = program byte address 3. sa x for sector-erase; uses a ms -a 7 address lines for sst29sf/vfxxx a ms = most significant address a ms = a 15 for sst29sf/vf512, a 16 for sst29sf/vf010, a 17 for sst29sf/vf020, and a 18 for sst29sf/vf040 4. the device does not remain in software product id mode if powered down. 5. with a ms -a 1 =0; sst manufacturer ? s id= bfh, is read with a 0 = 0, sst29sf512 device id = 20h, is read with a 0 = 1 sst29sf512 device id = 21h, is read with a 0 = 1 sst29sf010 device id = 22h, is read with a 0 = 1 sst29vf010 device id = 23h, is read with a 0 = 1 sst29sf020 device id = 24h, is read with a 0 = 1 sst29sf020 device id = 25h, is read with a 0 = 1 sst29sf040 device id = 13h, is read with a 0 = 1 sst29vf040 device id = 14h, is read with a 0 = 1 6. both software id exit operations are equivalent
8 preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 2001 silicon storage technology, inc. s71160-05-000 5/01 505 absolute maximum stress ratings (applied conditions greater than those listed under ? absolute maximum stress ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 c to +150 c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd + 0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd + 1.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 13.2v package power dissipation capability (ta = 25 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w through hold lead soldering temperature (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange for sst29sf512/010/020/040 range ambient temp v dd commercial 0 c to +70 c 5v10% industrial -40 c to +85 c 5v10% o perating r ange for sst29vf512/010/020/040 range ambient temp v dd commercial 0 c to +70 c 2.7-3.6v industrial -40 c to +85 c 2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf for 55 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 100 pf for 70 ns see figures 13, 14, and 15 table 5: dc o perating c haracteristics v dd = 5.0v10% for sst29sf xxx symbol parameter limits test conditions min max units i dd power supply current address input=v il /v ih , at f=1/t rc min v dd =v dd max read 20 ma ce#=oe#=v il , we#=v ih , all i/os open write 20 ma ce#=we#=v il , oe#=v ih i sb1 standby v dd current (ttl input) 3 ma ce#=v ih , v dd =v dd max i sb2 standby v dd current (cmos input) 100 a ce#=v ihc , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 ? v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 2.0 v v dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.4 v i ol =2.1 ?, v dd =v dd min v oh output high voltage 2.4 v i oh =-400 ?, v dd =v dd min t5.3 505
preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 9 2001 silicon storage technology, inc. s71160-05-000 5/01 505 table 6: dc o perating c haracteristics v dd = 2.7-3.6v for sst29vf xxx symbol parameter limits test conditions min max units i dd power supply current address input=v il /v ih , at f=1/t rc min v dd =v dd max read 20 ma ce#=oe#=v il , we#=v ih , all i/os open write 20 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 15 ? ce#=v ihc , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 ? v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 ?, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 ?, v dd =v dd min t6.5 505 table 7: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t7.1 505 table 8: c apacitance (ta = 25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t8.1 505 table 9: r eliability c haracteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t9.2 505
10 preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 2001 silicon storage technology, inc. s71160-05-000 5/01 505 ac characteristics table 10: r ead c ycle t iming p arameters v dd = 5v10% for sst29sf xxx and 2.7-3.6v for sst29vf xxx symbol parameter sst29sf/vfxxx-55 sst29sf/vfxxx-70 units min max min max t rc read cycle time 55 70 ns t ce chip enable access time 55 70 ns t aa address access time 55 70 ns t oe output enable access time 30 35 ns t clz 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. ce# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t chz 1 ce# high to high-z output 20 25 ns t ohz 1 oe# high to high-z output 20 25 ns t oh 1 output hold from address change 00ns t10.5 505 table 11: p rogram /e rase c ycle t iming p arameters v dd = 5v10%v for sst29sf xxx and 2.7-3.6v for sst29vf xxx symbol parameter min max units t bp byte-program time 20 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 40 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t sce chip-erase 100 ms t11.6 505
preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 11 2001 silicon storage technology, inc. s71160-05-000 5/01 505 figure 4: r ead c ycle t iming d iagram figure 5: we# c ontrolled p rogram c ycle t iming d iagram 505 ill f03.1 address a ms-0 dq 7-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a ms = most significant address a ms = a 15 for sst29sf/vf512, a 16 for sst29sf/vf010, a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040 505 ill f04.1 address a ms-0 dq 7-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 555 2aa 555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# we# t bp note: a ms = most significant address a ms = a 15 for sst29sf/vf512, a 16 for sst29sf/vf010, a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040
12 preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 2001 silicon storage technology, inc. s71160-05-000 5/01 505 figure 6: ce# c ontrolled p rogram c ycle t iming d iagram figure 7: d ata # p olling t iming d iagram 505 ill f05.1 address a ms-0 dq 7-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 555 2aa 555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# ce# t bp note: a ms = most significant address a ms = a 15 for sst29sf/vf512, a 16 for sst29sf/vf010, a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040 505 ill f06.1 address a ms-0 dq 7 dd# d# d we# oe# ce# t oeh t oe t ce t oes note: a ms = most significant address a ms = a 15 for sst29sf/vf512, a 16 for sst29sf/vf010, a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040
preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 13 2001 silicon storage technology, inc. s71160-05-000 5/01 505 figure 8: t oggle b it t iming d iagram figure 9: we# c ontrolled s ector -e rase t iming d iagram 505 ill f07.1 address a ms-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms = a 15 for sst29sf/vf512, a 16 for sst29sf/vf010, a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040 505 ill f10.2 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 55 20 55 aa 80 aa sa x oe# ce# six-byte code for sector-erase t se t wp note: the device also supports ce# controlled sector-erase operation. the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 11) a ms = most significant address a ms = a 15 for sst29sf/vf512, a 16 for sst29sf/vf010, a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040
14 preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 2001 silicon storage technology, inc. s71160-05-000 5/01 505 figure 10: we# c ontrolled c hip -e rase t iming d iagram figure 11: s oftware id e ntry and r ead 505 ill f17.2 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 55 10 55 aa 80 aa 555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 11) note: a ms = most significant address a ms = a 15 for sst29sf/vf512, a 16 for sst29sf/vf010, a 17 for sst29sf/vf020 and a 18 for sst29sf/vf040 505 ill f08.2 address a 14-0 dq 7-0 we# note: device id = 20h for sst29sf512, 22h for sst29sf010, 24h for sst29sf020, 13h for sst29sf040 21h for sst29vf512, 23h for sst29vf010, 25h for sst29vf020, 14h for sst29vf040 sw1 sw0 sw2 device id 555 2aa 555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa bf 55 aa 90 t ida
preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 15 2001 silicon storage technology, inc. s71160-05-000 5/01 505 figure 12: s oftware id e xit and r eset 505 ill f21.0 address a 14-0 dq 7-0 t ida t wp t whp we# sw0 sw1 sw2 555 2aa 555 three-byte sequence for software id exit and reset oe# ce# aa 55 f0
16 preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 2001 silicon storage technology, inc. s71160-05-000 5/01 505 figure 13: ac i nput /o utput r eference w aveforms for sst29sf xxx figure 14: ac i nput /o utput r eference w aveforms for sst29vf xxx figure 15: t est l oad e xamples 505 ill f11.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (3.0 v) for a logic ? 1 ? and v ilt (0 v) for a logic ? 0 ? . measurement reference points for inputs and outputs are v it (1.5 v dd ) and v ot (1.5 v dd ). input rise and fall times (10% ? 90%) are <10 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 505 ill f11.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ? 1 ? and v ilt (0.1 v dd ) for a logic ? 0 ? . measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 505 ill f12b.2 to tester to dut c l test load example for sst29vf512/010/020/040 505 ill f12.2 test load example for sst29sf512/010/020/040 to tester to dut c l r l low r l high v dd
preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 17 2001 silicon storage technology, inc. s71160-05-000 5/01 505 figure 16: b yte -p rogram a lgorithm 505 ill f13.1 start load data: aah address: 555h load data: 55h address: 2aah load data: a0h address: 555h load byte address/byte data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed
18 preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 2001 silicon storage technology, inc. s71160-05-000 5/01 505 figure 17: w ait o ptions 505 ill f14.0 wait t bp , t sce, or t se byte- program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte data# polling program/erase completed program/erase completed read byte is dq 7 = true data? read dq 7 byte- program/erase initiated byte- program/erase initiated
preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 19 2001 silicon storage technology, inc. s71160-05-000 5/01 505 figure 18: s oftware id c ommand f lowcharts 505 ill f15.1 load data: aah address: 555h software id entry command sequence load data: 55h address: 2aah load data: 90h address: 555h wait t ida read software id load data: aah address: 555h software id exit & reset command sequence load data: 55h address: 2aah load data: f0h address: 555h load data: f0h address: xxh return to normal operation wait t ida wait t ida return to normal operation
20 preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 2001 silicon storage technology, inc. s71160-05-000 5/01 505 figure 19: e rase c ommand s equence 505 ill f19.2 load data: aah address: 555h chip-erase command sequence load data: 55h address: 2aah load data: 80h address: 555h load data: 55h address: 2aah load data: 10h address: 555h load data: aah address: 555h wait t sce chip erased to ffh load data: aah address: 555h sector-erase command sequence load data: 55h address: 2aah load data: 80h address: 555h load data: 55h address: 2aah load data: 20h address: sa x load data: aah address: 555h wait t se sector erased to ffh
preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 21 2001 silicon storage technology, inc. s71160-05-000 5/01 505 device speed suffix1 suffix2 sst29x fxxx -xxx -x x -x x package modifier h = 32 pins numeric = die modifier package type n = plcc w = tsop (die up) (8mm x 14mm) p = pdip temperature range c = commercial = 0 c to +70 c i = industrial = -40 c to +85 c minimum endurance 4 = 10,000 cycles read access speed 55 = 55 ns 70 = 70 ns device density 512 = 512 kilobit 010 = 1 megabit 020 = 2 megabit 040 = 4 megabit voltag e s = 5v?0% v = 2.7-3.6v
22 preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 2001 silicon storage technology, inc. s71160-05-000 5/01 505 sst29sf512 valid combinations sst29sf512-55-4c-nh sst29sf512-55-4c-wh sst29sf512-70-4c-nh sst29sf512-70-4c-wh sst29sf512-70-4c-ph sst29sf512-55-4i-nh sst29sf512-55-4i-wh sst29sf512-70-4i-nh sst29sf512-70-4i-wh sst29vf512 valid combinations sst29vf512-55-4c-nh sst29vf512-55-4c-wh sst29vf512-70-4c-nh sst29vf512-70-4c-wh sst29vf512-55-4i-nh sst29vf512-55-4i-wh sst29vf512-70-4i-nh sst29vf512-70-4i-wh sst29sf010 valid combinations sst29sf010-55-4c-nh sst29sf010-55-4c-wh sst29sf010-70-4c-nh sst29sf010-70-4c-wh sst29sf010-70-4c-ph sst29sf010-55-4i-nh sst29sf010-55-4i-wh sst29sf010-70-4i-nh sst29sf010-70-4i-wh sst29vf010 valid combinations sst29vf010-55-4c-nh sst29vf010-55-4c-wh SST29VF010-70-4C-NH sst29vf010-70-4c-wh sst29vf010-55-4i-nh sst29vf010-55-4i-wh sst29vf010-70-4i-nh sst29vf010-70-4i-wh sst29sf020 valid combinations sst29sf020-55-4c-nh sst29sf020-55-4c-wh sst29sf020-70-4c-nh sst29sf020-70-4c-wh sst29sf020-70-4c-ph sst29sf020-55-4i-nh sst29sf020-55-4i-wh sst29sf020-70-4i-nh sst29sf020-70-4i-wh sst29vf020 valid combinations sst29vf020-55-4c-nh sst29vf020-55-4c-wh sst29vf020-70-4c-nh sst29vf020-70-4c-wh sst29vf020-55-4i-nh sst29vf020-55-4i-wh sst29vf020-70-4i-nh sst29vf020-70-4i-wh sst29sf040 valid combinations sst29sf040-55-4c-nh sst29sf040-55-4c-wh sst29sf040-70-4c-nh sst29sf040-70-4c-wh sst29sf040-70-4c-ph sst29sf040-55-4i-nh sst29sf040-55-4i-wh sst29sf040-70-4i-nh sst29sf040-70-4i-wh sst29vf040 valid combinations sst29vf040-55-4c-nh sst29vf040-55-4c-wh sst29vf040-70-4c-nh sst29vf040-70-4c-wh sst29vf040-55-4i-nh sst29vf040-55-4i-wh sst29vf040-70-4i-nh sst29vf040-70-4i-wh example: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations.
preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 23 2001 silicon storage technology, inc. s71160-05-000 5/01 505 packaging diagrams 32- pin p lastic l ead c hip c arrier (plcc) sst p ackage c ode : nh 32- pin t hin s mall o utline p ackage (tsop) 8 mm x 14 mm sst p ackage c ode : wh .030 .040 .013 .021 .490 .530 .075 .095 .015 min. .125 .140 top view side view bottom view 1 232 .026 .032 .400 bsc 32.plcc.nh-ill.2 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc. .050 bsc. .026 .032 .023 .029 .447 .453 .042 .048 .042 .048 optional pin #1 identifier .547 .553 .585 .595 .485 .495 .020 r. max. .106 .112 r. x 30? 32.tsop-wh-ill.4 note: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (.05) mm. 4. maximum allowable mold flash is 0.15mm at the packa g e ends, and 0.25mm between leads. 8.10 7.90 .270 .170 1.05 0.95 .50 bsc 0.15 0.05 12.50 12.30 pin # 1 identifier 14.20 13.80 0.70 0.50
24 preliminary specifications 512 kbit / 1 mbit / 2 mbit / 4 mbit small-sector flash sst29sf512 / sst29sf010 / sst29sf020 / sst29sf040 sst29vf512 / sst29vf010 / sst29vf020 / sst29vf040 ?2001 silicon storage technology, inc. s71160-05-000 5/01 505 32- pin p lastic d ual - in -l ine p ackage (pdip) sst p ackage c ode : ph 32.pdipph-ill.2 pin #1 identifier c l 32 1 base plane seating plane note: 1. complies with jedec publication 95 mo-015 ap dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches. .170 .200 7 ? 4 plcs. .600 bsc .100 bsc .120 .150 .016 .022 .045 .065 .070 .080 .015 .050 .065 .075 1.645 1.655 .008 .012 0 ? 15 ? .600 .625 .530 .550 silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.ssti.com

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